The present disclosure relates to a circuit arrangement for clock and data recovery, CDR, and to a method for CDR in communication systems.
In communication systems, in particular in packet based high-speed serial data communication systems, CDR may be used to extract a recovered clock signal and a recovered data signal from an input signal, in particular from a self-clocking input signal. That is, a clock is embedded in a transmitted data stream of the input signal. Therein, the extraction is for example realized by sampling the input signal using the recovered clock signal. In this way, CDR may avoid a potential clock skew for example between two physically separated data and clock channels.
For common CDR solutions an additional, for example external, precise reference clock source may be required. The reference clock source may for example be realized as an oscillator, in particular as a crystal oscillator. Several existing CDR solutions employ more than a single control loop, for example two control loops. These factors commonly represent drawbacks of existing solutions increasing for example cost, complexity, and/or size of a CDR arrangement. Other drawbacks of existing CDR circuit arrangements may include jitter, a lack of robust frequency acquisition and/or a lack of precise phase locking.